Academic Staff : Koichiro Mashiko

• Embedded System Design with emphasis on Mixed-Signal Design
• Design Methodology of LSI Chips and Systems
• Device Physics with emphasis on Memories

• April/1/2009 – Marcg/31/2015: General Manager and Director of Kobe Design Center, A-R-Tec Corp., Higashi-Hiroshima, Japan
• April/1/2008 – March/31/2009: Senior Manager, Planning of R&D, Renesas Technology, Inc. Itami Japan
• September/5/2002 – March/31/2008: Senior Researcher,　 STARC    (Semiconductor Technology Academic Research Center), Yokohama, Japan
• July/16/1993 – September/1/2002: Manager, Novel Circuit Architecture Group,  Mitsubishi Electric Corp. Itami, Japan.
• August/25/1990 – July/15/1993: Research Staff, Mitsubishi Electric Research Laboratories, Cambridge, U.S.A
• April/1/1977 – August/15/1990: Researcher, Mitsubishi Electric LSI Development Center, Itami, Japan

• Fifth Generation Computer Project (1988-1990)    (ICOT: Institute for new generation computer technology)      Sub Theme: “PSI（Personal Sequential Inference Machine）
• b)  Dream-Chip Project (2010-2011)   (ASET: Association of Super-Advanced Electronics Technology)    Sub Theme: “Ultra-wide Bus SiP 3D Integration Technology
  

• 1994-1998：    Program Committee @ IEEE VLSI Circuit Symposium
• 1999-2002：    Technical Committee @ IEEE CICC
• 2001-2002：    Voting Member @IEEE 802.3ae Committee(10Giga Ethernet)
• 2003-2005：    Topic Chairman and Program Committee @ IEEE ASP-DAC
• 2002-2009：    Program Committee @ IEEE VLSI-DAT(Taiwan)
• 2006-2009：    Program Committee @ IEEE A-SSCC

• 1988：    IR100 Award（256Kb Dual Port RAM）
• 1997：    R&D100 Award（1.9GHz IF Cordless Transceiver）
• 2000：    R&D100Award（2.5Gbps 0.18um SOI-CMOS Mux/Demux）

1. Invited Talk:  How to Design Low-Power Digital Cellular Phones
   K. Mashiko @International Symp. on Low Power Electronics and Devices pp.177-180, Aug-96.
2. Invited Talk: “Challenge and opportunity in analog and RF electronics,”
   K. Mashiko @ASICON 2005. 6th Int. Conf. on ASICs, Volume 1,
   pp.1205-1209, Oct-05.
3. Panelist @ ISSCC1987 Evening Discussion “DRAM Cell Structures and Technologies”, Feb-87.
4. Panelist @ ISSCC1998　Evening Discussion  “Deep Sub 1V, SOI or Bulk CMOS?”, Feb-98.
5. Organizer of Panel Discussion @ IEEE　AP-ASIC   “Academia/industry collaboration in SOC design education: Wishes and reality.”, June-04.

b) Journal
International Referred Journal

1. K. Mashiko, T. Kobayashi, H. Miyamoto, K. Arimoto, Y. Morooka,
   M. Hatanaka, M. Yamada and T. Nakano, “A 70ns 256K DRAM with Bit-Line
   Shield,”  IEEE Journal of Solid-State Circuits, Vol.SC-19, No.5, pp.591-596,
   Oct-84.
2. K. Mashiko, M. Ngamoto, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa,
   T. Yoshihara and T. Nakano, “A 4-Mbit DRAM with Folded-Bitline Adaptive Sidewall-Isolated Capacitor (FASIC) Cell,”  IEEE Journal of Solid-State Circuits, Vol.SC-22, No.5, pp.643-650, Oct-87.
3. T. Nakura, K. Ueda, K. Kubo, Y. Matsuda, K. Mashiko and T. Yoshihara,
   “A 3.6-Gb/s 340-mW 16:1 Pipe-Lined Multiplexer using 0.18 μm SOI-CMOS Technology,” IEEE Journal of Solid-State Circuits, Vol.35, NO.5, pp.751-756, May-00.
4. S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano,
   T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa and M. Inuishi, “Feasibility of 0.18 μm SOI CMOS Technology Using Hybrid Trenh Isolation with High Resistivity Substrate for Embedded RF/Analog Applications,” IEEE Transactions on Electron Devices, Vol.48, No.9, pp.2065-2073, Sep-01.
   (and about 20 papers more)

Other Journal

1. K. Mashiko, K. Ueda, T. Yoshimura, T. Hirota, Y. Wada, J. Takasoh and K. Kubo, “Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits, “IEICE Trans. Electron, Vol.E-83-C, No.11, pp.1697-1704, Nov-00.
2. Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, M. Inuishi and T. Nishimura, “Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application,”  IEICE Trans. Electron, Vol.E84-C, N0.12, pp.1735-1745, Dec-01.
3. H. SAN, A. HAYAKAWA, Y. JINGU, H. WADA, H. HAGIWARA, K. KOBAYASHI, H. KOBAYASHI, T. MATSUURA, K. YAHAGI, J. KUDOH, H. NAKANE, M. HOTTA, T. TSUKADA, K. MASHIKO, and A. WADA, “Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout IEICE Trans Fundamentals, Vol.E89-A, No.4, pp.908-915, Apr-06.

(and about 20 papers more)

c) Book/Book Chapter

1. 1  “Neuro-computer Engineering” Chapter 5, Kogyo Chousakai, 1992.
   2  “System LSI: Application and Technology”, Chapter 8、Science Forum, 2000.
   3　”Digital Systems Engineering (translation)”, Chapter 1,2,4, Maruzen, 2003.
   Original: “Digital Systems Engineering;” by William J. Dally & John W. Poulton)

d) Proceedings of International Conference

1. K. Mashiko, T. Kobayashi, W. Wakamiya, M. Hatanaka and M. Yamada, “A 70ns 256K DRAM with Bitline Shielding Structure,” ISSCC Dig. Tech. Papers, pp.98-99, Feb-84.
2. K. Mashiko, Y. Morooka, K. Yasuda, T. Kobayashi, M. Yamada and T. Nakano, “A CMOS Dual Port Memory with Serial Read/Write Function for Graphic Systems,” IEEE Transactions on Consumer Electronics, Vol.CE-32, No.3, pp.636-643, Aug-86.
3. K. Arimoto, T. Yamagata, H. Miyamoto, K. Mashiko, M. Yamada, S. Sato and H. Shibata, “AN EFFECT OF FILLER-INDUCED-STRESS TO DRAM SENSE AMPLIFIER,” VLSI Symposium Dig. Technical Papers, pp.92-93, Jun-85.
4. K. Mashiko, M. Nagatomo, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa, T. Yoshihara and T. Nakano, “A 90ns 4Mb DRAM in a 300mil DIP,” ISSCC Dig. Tech. Papers, pp.12-13, Feb-87.
   (and more than 22 papers more)