Academic Staff : Chia Yee

Ooi Chia Yee BEng (UTM), MEng (UTM), PhD Information Science (NAIST. Japan)
	Senior Lecturer Email:ooichiayee@ic.utm.my Tel: 03 2203 1237
Research Interests	Semiconductor Fault Modelling Test Pattern Generation Design for Testability System-on-Chip Design, Test and Verification
Professional Membership	IEEE
Grants	Project leader: Research University Grant, Vote No. 00J03 (2011-2012). Multi-Constrained System-on-Chip (SoC) Test Planning Framework based on Enhanced 3-DFloorplanning Project leader: MJIIT Grant, Vote No. 04J14 (2011-2014). A Dependable System-on-Chip Architecture for Image Processing Project leader: MOSTI Sciencefund Grant, Vote No. 4S013 (2012-2013). Adaptive Online Testing for MPEG Processing on Network-on-Chip Co-researcher: Intel Grant, Vote No. 4C016 (2011-2012). Adaptive Online Concurrent Network-on-Chip Testing Mechanism
Previous Positions	N/A
Activities	Organizing Committee Member. Asian Control Conference 2015. Programme Committee Member. Asian Test Symposium 2012. Reviewer. International Journal. Computers and Electrical Engineering in 2012. Editorial board. ELEKTRIKA. Journal of Electrical Engineering. Faculty of Electrical Engineering, UTM in 2012.
Selected Publications	Journals C.Y. Ooi, J.P. Sua and S.C. Lee, “Power-Aware System-on-Chip Test Scheduling using Enhanced Rectangle Packing Algorithm,” 2012 (In Press). C.Y. Ooi and H. Fujiwara, “A New Design-for-Testability Method based on Thru-Testability,” Journal of Eletronic Testing: Theory and Application: Volume 27, Issue 5, 2011, pp. 583-598. N. Paraman, C.Y. Ooi, A.Z. Sha’ameri and H. Fujiwara, “A New Class of Easily Testable Assignment Decision Diagrams,” Malaysian Journal of Computer Science, Vol. 23, June 2010, No. 1, pp. 1-17. N. Oka, C.Y. Ooi, H. Ichihara, T. Inoue and H. Fujiwara, “Test Generation for Sequential Circuits with Partial Thru Testability,” Trans. Of IEICE on Information and Systems, Dec. 2009, pp. 2207-2216. H. Fujiwara, H. Iwata, T. Yoneda, C.Y. Ooi, “A Non-Scan Design-for-Testability for Register Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Model,” IEEE Trans. of Computer Aided Design of Integrated Systems and Circuits, Sept.2008, pp. 1535-1544. C.Y. Ooi, T. Clouqueur and H. Fujiwara, “Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation,” Trans. of IEICE on Information and Systems, Aug. 2007, pp. 1202-1212. C.Y. Ooi, T. Clouqueur and H. Fujiwara, “Classification of Sequential Circuits Based on tkNotation and Its Applications,” Trans. of IEICE on Information and Systems, Dec.2005, pp. 2738-2747