{"id":4305,"date":"2019-03-11T06:23:23","date_gmt":"2019-03-11T06:23:23","guid":{"rendered":"http:\/\/mjiit.utm.my\/?p=4305"},"modified":"2019-03-11T06:23:23","modified_gmt":"2019-03-11T06:23:23","slug":"academic-staff-koichiro-mashiko","status":"publish","type":"post","link":"https:\/\/mjiit.utm.my\/mjiit2025\/academic-staff-koichiro-mashiko\/","title":{"rendered":"Academic Staff : Koichiro Mashiko"},"content":{"rendered":"
\n\n\n\n\n\n\n\n\n\n\n
Prof Koichiro Mashiko <\/strong>
\nPhD (Osaka University, Japan)<\/a><\/span><\/td>\n<\/tr>\n
\"\"<\/a><\/td>\nProfessor
\nElectronic Systems Engineering Department<\/strong>
\nEmail: k.mashiko@utm.my<\/a>
\nTel:03 2203 1307<\/td>\n<\/tr>\n
Research Interests<\/strong><\/td>\n\n
    \n
  • Embedded System Design with emphasis on Mixed-Signal Design<\/li>\n
  • Design Methodology of LSI Chips and Systems<\/li>\n
  • Device Physics with emphasis on Memories<\/li>\n<\/ul>\n<\/td>\n<\/tr>\n
Previous Position<\/strong><\/td>\n\n
    \n
  • April\/1\/2009 \u2013 Marcg\/31\/2015: General Manager and Director of Kobe Design Center, A-R-Tec Corp., Higashi-Hiroshima, Japan<\/li>\n
  • April\/1\/2008 \u2013 March\/31\/2009: Senior Manager, Planning of R&D, Renesas Technology, Inc. Itami Japan<\/li>\n
  • September\/5\/2002 \u2013 March\/31\/2008: Senior Researcher,\u3000 STARC\u00a0\u00a0 \u00a0(Semiconductor Technology Academic Research Center), Yokohama, Japan<\/li>\n
  • July\/16\/1993 \u2013 September\/1\/2002: Manager, Novel Circuit Architecture Group,\u00a0 Mitsubishi Electric Corp. Itami, Japan.<\/li>\n
  • August\/25\/1990 \u2013 July\/15\/1993: Research Staff, Mitsubishi Electric Research Laboratories, Cambridge, U.S.A<\/li>\n
  • April\/1\/1977 \u2013 August\/15\/1990: Researcher, Mitsubishi Electric LSI Development Center, Itami, Japan<\/li>\n<\/ul>\n<\/td>\n<\/tr>\n
Grants<\/strong><\/td>\n\n
    \n
  • Fifth Generation Computer Project (1988-1990)\u00a0\u00a0\u00a0 (ICOT: Institute for new generation computer technology)\u00a0\u00a0\u00a0\u00a0\u00a0 Sub Theme: \u201cPSI\uff08Personal Sequential Inference Machine\uff09<\/li>\n
  • b)\u00a0 Dream-Chip Project (2010-2011)\u00a0\u00a0 (ASET: Association of Super-Advanced Electronics Technology)\u00a0\u00a0\u00a0 Sub Theme: \u201cUltra-wide Bus SiP 3D Integration Technology
    \n<\/strong><\/li>\n<\/ul>\n<\/td>\n<\/tr>\n
Activities<\/strong><\/td>\nChairman\/Committee Member<\/p>\n
    \n
  • 1994-1998\uff1a\u00a0\u00a0 \u00a0Program Committee @ IEEE VLSI Circuit Symposium<\/li>\n
  • 1999-2002\uff1a\u00a0\u00a0 \u00a0Technical Committee @ IEEE CICC<\/li>\n
  • 2001-2002\uff1a\u00a0\u00a0 \u00a0Voting Member @IEEE 802.3ae Committee(10Giga Ethernet)<\/li>\n
  • 2003-2005\uff1a\u00a0\u00a0 \u00a0Topic Chairman and Program Committee @ IEEE ASP-DAC<\/li>\n
  • 2002-2009\uff1a\u00a0\u00a0 \u00a0Program Committee @ IEEE VLSI-DAT(Taiwan)<\/li>\n
  • 2006-2009\uff1a\u00a0\u00a0 \u00a0Program Committee @ IEEE A-SSCC<\/li>\n<\/ul>\n<\/td>\n<\/tr>\n
Awards<\/strong><\/td>\n\n
    \n
  • 1988\uff1a\u00a0\u00a0 \u00a0IR100 Award\uff08256Kb Dual Port RAM\uff09<\/li>\n
  • 1997\uff1a\u00a0\u00a0 \u00a0R&D100 Award\uff081.9GHz IF Cordless Transceiver\uff09<\/li>\n
  • 2000\uff1a\u00a0\u00a0 \u00a0R&D100Award\uff082.5Gbps 0.18um SOI-CMOS Mux\/Demux\uff09<\/li>\n<\/ul>\n<\/td>\n<\/tr>\n
Selected Publications<\/strong><\/td>\na) Keynote\/Invited<\/p>\n
    \n
  1. Invited Talk:\u00a0 How to Design Low-Power Digital Cellular Phones
    \nK. Mashiko @International Symp. on Low Power Electronics and Devices pp.177-180, Aug-96.<\/li>\n
  2. Invited Talk: \u201cChallenge and opportunity in analog and RF electronics,\u201d
    \nK. Mashiko @ASICON 2005. 6th Int. Conf. on ASICs, Volume 1,
    \npp.1205-1209, Oct-05.<\/li>\n
  3. Panelist @ ISSCC1987 Evening Discussion \u201cDRAM Cell Structures and Technologies\u201d, Feb-87.<\/li>\n
  4. Panelist @ ISSCC1998\u3000Evening Discussion\u00a0 \u201cDeep Sub 1V, SOI or Bulk CMOS?\u201d, Feb-98.<\/li>\n
  5. Organizer of Panel Discussion @ IEEE\u3000AP-ASIC\u00a0\u00a0 \u201cAcademia\/industry collaboration in SOC design education: Wishes and reality.\u201d, June-04.<\/li>\n<\/ol>\n

    b) Journal
    \nInternational Referred Journal<\/p>\n

      \n
    1. K. Mashiko, T. Kobayashi, H. Miyamoto, K. Arimoto, Y. Morooka,
      \nM. Hatanaka, M. Yamada and T. Nakano, \u201cA 70ns 256K DRAM with Bit-Line
      \nShield,\u201d\u00a0 IEEE Journal of Solid-State Circuits, Vol.SC-19, No.5, pp.591-596,
      \nOct-84.<\/li>\n
    2. K. Mashiko, M. Ngamoto, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa,
      \nT. Yoshihara and T. Nakano, \u201cA 4-Mbit DRAM with Folded-Bitline Adaptive Sidewall-Isolated Capacitor (FASIC) Cell,\u201d\u00a0 IEEE Journal of Solid-State Circuits, Vol.SC-22, No.5, pp.643-650, Oct-87.<\/li>\n
    3. T. Nakura, K. Ueda, K. Kubo, Y. Matsuda, K. Mashiko and T. Yoshihara,
      \n\u201cA 3.6-Gb\/s 340-mW 16:1 Pipe-Lined Multiplexer using 0.18 \u03bcm SOI-CMOS Technology,\u201d IEEE Journal of Solid-State Circuits, Vol.35, NO.5, pp.751-756, May-00.<\/li>\n
    4. S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano,
      \nT. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa and M. Inuishi, \u201cFeasibility of 0.18 \u03bcm SOI CMOS Technology Using Hybrid Trenh Isolation with High Resistivity Substrate for Embedded RF\/Analog Applications,\u201d IEEE Transactions on Electron Devices, Vol.48, No.9, pp.2065-2073, Sep-01.
      \n(and about 20 papers more)<\/li>\n<\/ol>\n

      Other Journal<\/p>\n

        \n
      1. K. Mashiko, K. Ueda, T. Yoshimura, T. Hirota, Y. Wada, J. Takasoh and K. Kubo, \u201cUltra Low Power Operation of Partially-Depleted SOI\/CMOS Integrated Circuits, \u201cIEICE Trans. Electron, Vol.E-83-C, No.11, pp.1697-1704, Nov-00.<\/li>\n
      2. Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, M. Inuishi and T. Nishimura, \u201cPartially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application,\u201d\u00a0 IEICE Trans. Electron, Vol.E84-C, N0.12, pp.1735-1745, Dec-01.<\/li>\n
      3. H. SAN, A. HAYAKAWA, Y. JINGU, H. WADA, H. HAGIWARA, K. KOBAYASHI, H. KOBAYASHI, T. MATSUURA, K. YAHAGI, J. KUDOH, H. NAKANE, M. HOTTA, T. TSUKADA, K. MASHIKO, and A. WADA, \u201cComplex Bandpass \u0394\u03a3AD Modulator Architecture without I, Q-Path Crossing Layout IEICE Trans Fundamentals, Vol.E89-A, No.4, pp.908-915, Apr-06.<\/li>\n<\/ol>\n

        (and about 20 papers more)<\/p>\n

        c) Book\/Book Chapter<\/p>\n

          \n
        1. 1\u00a0 \u201cNeuro-computer Engineering\u201d Chapter 5, Kogyo Chousakai, 1992.
          \n2\u00a0 \u201cSystem LSI: Application and Technology\u201d, Chapter 8\u3001Science Forum, 2000.
          \n3\u3000\u201dDigital Systems Engineering (translation)\u201d, Chapter 1,2,4, Maruzen, 2003.
          \nOriginal: \u201cDigital Systems Engineering;\u201d by William J. Dally & John W. Poulton)<\/li>\n<\/ol>\n

          d) Proceedings of International Conference<\/p>\n

            \n
          1. K. Mashiko, T. Kobayashi, W. Wakamiya, M. Hatanaka and M. Yamada, \u201cA 70ns 256K DRAM with Bitline Shielding Structure,\u201d ISSCC Dig. Tech. Papers, pp.98-99, Feb-84.<\/li>\n
          2. K. Mashiko, Y. Morooka, K. Yasuda, T. Kobayashi, M. Yamada and T. Nakano, \u201cA CMOS Dual Port Memory with Serial Read\/Write Function for Graphic Systems,\u201d IEEE Transactions on Consumer Electronics, Vol.CE-32, No.3, pp.636-643, Aug-86.<\/li>\n
          3. K. Arimoto, T. Yamagata, H. Miyamoto, K. Mashiko, M. Yamada, S. Sato and H. Shibata, \u201cAN EFFECT OF FILLER-INDUCED-STRESS TO DRAM SENSE AMPLIFIER,\u201d VLSI Symposium Dig. Technical Papers, pp.92-93, Jun-85.<\/li>\n
          4. K. Mashiko, M. Nagatomo, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa, T. Yoshihara and T. Nakano, \u201cA 90ns 4Mb DRAM in a 300mil DIP,\u201d ISSCC Dig. Tech. Papers, pp.12-13, Feb-87.
            \n(and more than 22 papers more)<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

             <\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

            Prof Koichiro Mashiko PhD (Osaka University, Japan) Professor Electronic Systems Engineering Department Email: k.mashiko@utm.my Tel:03 2203 1307 Research Interests Embedded System Design with emphasis on Mixed-Signal Design Design Methodology of […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_et_pb_use_builder":"","_et_pb_old_content":"","_et_gb_content_width":"","ngg_post_thumbnail":0,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-4305","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"acf":[],"_links":{"self":[{"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/posts\/4305","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/comments?post=4305"}],"version-history":[{"count":0,"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/posts\/4305\/revisions"}],"wp:attachment":[{"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/media?parent=4305"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/categories?post=4305"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mjiit.utm.my\/mjiit2025\/wp-json\/wp\/v2\/tags?post=4305"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}