• Phase-Locked Loop

    PLL now finds its application everywhere.  However, in low frequencies, its responsiveness is not enough, leading to degraded performance.  In addition, jitter, fluctuation in output, poses problems in high-spec

    applications.  Our research on PLL proposes solutions to these two. The first problem is solved by “time-optimal PLL,” featuring very fast responses, using a completely new configuration.  Although it was already realized as a commercial USB audio adapter, its improvement is still continuing. The second, jitter, is now investigated using “pulse interpolation,” and will find its application such as in digital TVs.

    Dynamically Reconfigurable Systems

    Circuit has been a fixed entity.  However, since FPGA, field programmable gate array, was introduced, one universal circuit can be “configured” to realize a particular need.  By extending this property into “dynamic” or “in-operation” arena, for example, Sony solid-state Walkman features reduction in circuit size and power.

    Our research on dynamic reconfiguration is expected to derive both dramatic circuit reduction and fast operation by making use of fundamentally different scheme. This research now attracts attention in space application under severe space ray environment.  It is also expected to be used in survey of nuclear plant like Fukushima.

    Thermal-Aware & Power-Aware Design-for-Testability

    Test power has been turned to a bottleneck for test considerations as the excessive average and peak power dissipation along with energy consumed during test mode have serious negative effects on chip reliability. Moreover, it can increase package test cost, heat damage and even yield loss. Reduced test power contributes to the improvement of battery lifetime particularly in portable electronic devices with periodic self test ability. Our research focus on low-power design-for-testability including those for scan chain architecture whereby dynamic power in both scan chain and combinational part during capture and shift modes are reduced. Besides, overcoming thermal issues for system-on-chip test scheduling is also our research focus. This is important to avoid hotspots that might damage the system. DFT techniques for system-on-chip that utilizes network-on-chip as communication mean are also emphasized by this research laboratory.