Publication

1. Sieng Wong, C. Y. Ooi, Y. W. Hau, M. N. Marsono, N. S. Husin, “Feasible Transition Path Generation for EFSM-based System Testing,” in Proc. ISCAS 2013, Beijing, 2013.
2. A. C. Abdullah and C. Y. Ooi, “Study on Test Compaction in High-level Automatic Test Pattern Generation (ATPG) Platform,” Circuits and Systems, Scientific Research, August 2013.
3. C. Y. Ooi, J. P. Sua and S. C. Lee, “Power-Aware System-on-Chip Test Scheduling using Enhanced Rectangle Packing Algorithm,” Computers and Electrical Engineering, Elsevier, pp. 1444-1455, 2012.
4. Machida, Inoue, Kobayashi: “Highly precise rotational speed control by a hybrid of PLL and repetitive control”, Trans. IEE Japan, vol.132C, No.5 to appear, 2012, in Japanese
5. C. Y. Ooi and H. Fujiwara, “A New Design-for-Testability Method based on Thru-Testability,” Journal of Electronic Testing: Theory and Application, Springer, pp. 583-598, 2011.
6. N. Paraman, C. Y. Ooi, A. Z. Sha’ameri, and H. Fujiwara, “Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram,” in Workshop on RTL and High Level Testing, pp. 9-15, 2011.
7. Machida, Kambara, Tanaka, Kobayashi: “A motor speed servo system based on the dual-loop PLL”, Trans. IEE Japan, vol.131C, pp.337-342, 2011, in Japanese